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often there is a need for a simple and
inexpensive method of pre-screening CMOS logic
integrated circuits before they are installed in
a circuit board assembly. Pre-testing these IC's
is especially beneficial when they are to be
installed into surface mount assemblies or
multi-chip modules (MCM). Troubleshooting can be
very difficult and replacement is often harmful
to the board assembly.
This application note describes
a method of testing CMOS logic gates that is very
simple and easy to implement. Because the
requirements for each particular application will
vary, this example uses a 74HCT86 CMOS XOR gate
package for illustration only. Other types of
logic IC's could be tested using similar methods.
The test parameters would be different, and
input/output lines may change, but the
methodology would remain pretty much the same. By
studying this example, and seeing how the FT-100
is used to control the device under test and
measure the ultra-low currents, it should be
relatively easy to derive your own tests.
Because this test needs more
analog input lines than the FT-100 main unit can
provide, we are using a 1504 Expansion Module,
which gives us 16 extra analog inputs with an
input range of 0-5 volts. Other expansion modules
could be used as well, but the 1504 is the least
expensive Expansion Module that can accomplish
our task.
Test Requirements
The test parameters for our IC
are the following:
- With no load on the outputs
and all inputs set to zero volts, the overall
device current must be
less than 10
microamps.
- Current for each gate input
must be less than 1 microamp.
- Each gate output must be able
to sink and source 4 ma. - Gates must have the
proper logic
output.
- Test must stop on the first
defect. No need to test remainder of device if
there is a defect.
These parameters will obviously
change with each type of device and especially
with a different family type. Once again, the
74HCT86, and these parameters, are used only as
an example.
Circuit Description
Refer to the overall schematic
in figure 1. In order to measure current, we must
convert the current into a voltage by feeding it
through a resistor of known value. We can then
measure the voltage drop across the resistor and
mathematically determine the current (remember
Ohms law?). The resistors should be high
precision (1% or better), and depending on
individual tolerance requirements, they may need
to be adjustable for very fine calibration. Since
the overall current to the device must be less
than 10 microamps, we can insert a 100K ohm
resistor (R17) in series with the VCC line and
measure the voltage drop across the resistor. If
the voltage is greater than 1.0 volts, we know
the device current is over 10 microamps. To
insure that VCC does not drop or change during
the other tests, we use digital output line LA9
and a diode to provide a higher current VCC.
In a similar fashion we test
the gate input currents by inserting a 1 Megohm
resistor in series with each input. By measuring
the voltage drop across the input resistors, we
can derive the input current. This current must
be less than 1 microamp, so the voltage across
the 1 Megohm resistor must be less than 1.0 volt.
The gate inputs can be driven high or low with
the input current tested in both configurations.
The gate outputs must be able
to sink and source at least 4 ma. To test this,
we place a resistor load across each gate output
and test the output voltage. This allows us to
"connect" pull-up or pull-down
resistors of know value and determine the output
current drive capabilities.
Hopefully, this test example
will be sufficient to show how the FT-100 can be
used to measure very small currents when
necessary. Inserting series resistors in the gate
inputs will obviously "slow" the
overall gate reaction. If this is a problem, a
small delay may be necessary in the test program
after each input setup to give the gate input
voltage time to reach its ultimate level. If the
gate must operate at full speed, it would be very
easy to use analog switches, such as the DG202 to
effectively bypass the series resistance. If this
is a concern, contact Y-tek for applications
assistance.
If you have components to test
and aren't sure how to go about setting it up or
how the FT-100 can be used, give us a call at
Y-tek. An Applications Engineer will be glad to
help you.
FIGURE 1
- Schematic of CMOS digital gate test fixture
FIGURE 2 - Program
Listing
GATE_TST
'Program Name
'
' This test program will functionally test the
designated CMOS gate for proper operation,
' and also
measure the following:
' - Current drain
on each input line.
' - Overall
current drain on the VCC line.
' - Output sink
and source voltage from each gate with and
without a designated load.
'
' All test
results will be printed on a serial printer (or
sent to a data terminal or
' computer). The
LCD display will be used only for operator
instruction.
'
'
D$=">>> DEFECT! <<< "
'
FOR X=0 TO 3:READ Q(X):NEXT
'Read in the
correct logic output for gate under test
DATA 0,1,1,0
'Data for gate under test
'
BEG:
PRINT:PRINT:PRINT "* * * * * * * * XOR GATE
IC TEST * * * * * * * *"
'Print header
'
'----------
Initialize all I/O lines to a known state
------------
LA9=0
'LA9 acts as a high current VCC source.
LA10=0
'LA10 acts as the low current VCC source.
PA1=10101010B
'This removes all sink and source load from the
gate output.
FOR X=1 TO 8:AA(X)=0:NEXT 'Set
analog output lines to 0.0 volts.
'
'------ Instruct
operator that test is ready to run ------
LS: DISP
"Insert IC, then": DISP "Press
YES": DISP "Press NO to":DISP
"end test."
L0: IF NO
THEN CLS:END 'End of test IF YES=0 THEN GOTO L0
'Wait for YES to be pressed.
'
'
'--- TEST #1:
Measure the current drawn by VCC line & test
for less than 10 micro-amps ---
LA10=1
'Turn on low current VCC
IF AB13>4 THEN GOTO L1
'Test for more
than 1 volt drop across R17
LA10=0
'Turn off low current VCC
PRINT D$;"Overcurrent on VCC line! VCC
current = ";(5-AA13)/0.1;"
micro-amps"
GOTO DEFECT
'Go to defect handling routine.
'
'
'--- TEST #2:
Test gates for proper logic output ---
LA9=1 'Turn on high current VCC
L1: FOR
GATE=1 TO 8
'Gate counter
FOR X=0 TO 3
AA(GATE)=(X AND 1B)*5: AA(GATE+1)=(X AND 10B)*5
'Set two gate inputs
IF Q(X)=INT (AB(GATE+8)/4.0) THEN GOTO L2
PRINT D$;"Gate #";GATE-INT(GATE/2);
'Gate defect
PRINT ": Inputs =";X AND 1;"
";X AND 10B;" Output
=";AA(GATE+8);" Should =";Q(X)
X=3:GATE=8:NEXT:NEXT:GOTO DEFECT
'Abort test
L2: NEXT
INC GATE:NEXT
'Done with all gates?
FOR X=1 TO 8:AA(X)=0:NEXT
'Set all gate inputs back to zero
'
'
'--- TEST #3:
Measure & Test input current at gate inputs
for less than 1 micro-amp ---
'(First test
source input current)
FOR LINE=1 TO 8
'Test all 8 inputs
AA(LINE)=5:IF (AA(LINE)-AB(LINE))<1.0 THEN
GOTO L3 'Voltage across resistor < 1.0 v.?
PRINT D$;"Gate #";LINE-INT(LINE/2);
PRINT " Over-current! Gate input drive =
high."
PRINT " Current at AA";LINE;" is:
";AA(LINE)-AB(LINE);" micro-amps."
LINE=8:NEXT:GOTO DEFECT
'Abort test
L3: NEXT
' (Now test sink
input current)
FOR LINE=1 TO 8
'Test all 8 inputs
AA(LINE)=0:IF (AB(LINE)-AA(LINE))<1.0 THEN
GOTO L4 'Voltage across resistor < 1.0 v.?
PRINT D$;"Gate #";LINE-INT(LINE/2);
PRINT "Over-current! Gate input drive =
low."
PRINT " Current at AA;"LINE;" is:
";AB(LINE)-AA(LINE);" micro-amps."
LINE=8:NEXT:GOTO DEFECT
'Abort test
L4: NEXT
'
'
'--- TEST #4:
Test gate outputs for proper current drive
capabilities ---
'
' (First turn on
pull-up resistors & test for sink current)
PA1=0FFH
'Turn
on pull-up loads on gate outputs
FOR GATE=1 TO 4 'Test all 4 gates
IF AB(GATE+8)<=0.4 THEN GOTO
L5
'Test output voltage
PRINT D$;"Gate #";GATE;" With
pull-up resistor, output should be 'low'."
PRINT " Output =";AB(GATE+8);"
volts."
GATE=8:NEXT:GOTO
DEFECT
'Abort test
L5: NEXT
'
' (Now turn on
pull-down resistors & test for source
current)
PA1=0
'Turn
on pull-down loads on gate outputs
FOR X=1 TO 8:AA(X)=5:INC
X:NEXT
'Set gate inputs to yield 1 on output
FOR GATE=1 TO 4
'Test all 4 gates
IF AB(GATE+8)>=4.1 THEN GOTO
L6
'Test output voltage
PRINT D$;"Gate #";GATE;" With
pull-down resistor, output should be
'high'."
PRINT " Output =";AB(GATE+8);"
volts."
GATE=4:NEXT:GOTO
DEFECT
'Abort test
L6: NEXT
'
PRINT
"<<<< PASSED
>>>>" GOTO EOT
'End of test -
<<PASSED>>
'
'
'
'-----------
Defect Routine -----------
DEFECT: FOR X=1
TO 4:BEEP 5000,50:DELAY 20:NEXT
'Alarm signal
EOT: PRINT
"----------------------- END OF TEST
-----------------------"
GOTO BEG
'
/
NOTICE: Every effort has
been made to insure the accuracy of the
information contained in this document, however
Y-tek is not responsible for any consequences
resulting from erroneous or inaccurate
information.
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